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toshiba tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 1 4,194,304 word x 4 bit dynamic ram description the tc5117400bsj/bst is the new generation dynamic ram organized 4,194,304 word by 4 bits. the tc5117400bsj/bst uti- lizes toshibas cmos silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. multiplexed address inputs permit the tc5117400bsj/bst to be packaged in a 26/24 pin plastic soj (300mil), and 26/24 pin plastic tsop (300mil). the package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. system oriented features include single power supply of 5v 10% tolerance, direct interfacing capability with high performance logic families such as schottky ttl. features 4,194,304 word by 4 bit organization fast access time and cycle time single power supply of 5v 10% with a built-in v bb generator low power - 605mw max. operating - (tc5117400bsj/bst-60) - 523mw max. operating - (tc5117400bsj/bst-70) - 5.5mw max. standby outputs unlatched at cycle end allows two- dimensional chip selection common i/o capability using ?arly write? operation read-modify-write, cas before ras refresh, ras -only refresh, hidden refresh, fast page mode and test mode capability all inputs and outputs ttl compatible 2048 refresh cycles/32ms package tc5117400bsj: soj26-p-300c tc5117400bst: tsop26-p-300d key parameters item tc5117400bsj/bst -60 -70 t rac ra s access time 60ns 70ns t aa column address access time 30ns 35ns t cac cas access time 15ns 20ns t rc cycle time 110ns 130ns t pc fast page mode cycle time 40ns 45ns preliminary 1. this technical data may be controlled under u.s. export administration regulations and may be subject to the approval of the u.s. department of commerce prior to export. any export or re-export, directly or indi- rectly, in contravention of the u.s. export administration regulations is strictly prohibited. 2. life support policy toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate of?er of toshiba america, inc. life support sys- tems are either systems intended for surgical implant in the body or systems which sustain life. a critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness. 3. the information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. all information in this data book is subject to change without prior notice. furthermore, toshiba cannot assume responsibility for the use of any license under the patent rights of toshiba or any third parties.
tc5117400bsj/bst-60/70 standard dram dr16040794 2 toshiba america electronic components, inc . preliminary pin name pin connection (top view) a0 ~ a10 address inputs ras row address strobe cas column address strobe we write enable oe output enable i/o1~i/o4 data input/output v cc power (+5v) v ss ground
dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 3 preliminary block diagram absolute maximum ratings item symbol rating unit note input voltage v in -0.5~v cc +0.5 v 1 output voltage v out -0.5~v cc +0.5 v 1 power supply voltage v cc -0.5~7.0 v 1 operating temperature t opr 0~70 c 1 storage temperature t stg -55~150 c1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 900 mw 1 short circuit output current i out 50 ma 1
tc5117400bsj/bst-60/70 standard dram dr16040794 4 toshiba america electronic components, inc . preliminary recommended dc operating conditions (ta = 0 ~ 70 c) *v cc + 2.0v at pulse width 20ns (pulse width is measured at v cc ). **-2.0v at pulse width 20ns (pulse width is measured at v ss ). dc electrical characteristics (v cc = 5v 10%, ta = 0 ~ 70 c) symbol parameter min. typ. max. unit note v cc power supply voltage 4.5 5.0 5.5 v 2 v ih input high voltage 2.4 - v cc + 0.5* v 2 v il input low voltage -0.5** - 0.8 v 2 symbol parameter min max unit note | cc1 operating current average power supply operating current (ras , cas , address cycling: t rc =t rc min) tc5117400bsj/bst-60 - 110 ma 3,4 5 tc5117400bsj/bst-70 - 95 | cc2 standby current power supply standby current (ras =cas =v ih ) ?ma | cc3 ras only refresh current average power supply current, ras only mode (ras cycling, cas =v ih : t rc =t rc min.) tc5117400bsj/bst-60 - 110 ma 3, 5 tc5117400bsj/bst-70 - 95 | cc4 fast page mode current average power supply current, fast page mode (ras =v il , cas , address cycling: t pc =t pc min.) tc5117400bsj/bst-60 - 70 ma 3,4 5 tc5117400bsj/bst-70 - 60 | cc5 standby current power supply standby current (ras =cas =v cc -0.2v) ?ma | cc6 cas before ras refresh current average power supply current, cas before ras mode (ras , cas , cycling: t rc =t rc min.) tc5117400bsj/bst-60 - 110 ma 3, 5 tc5117400bsj/bst70 - 95 | i (l) input leakage current input leakage current, any input (0v dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 5 preliminary electrical characteristics and recommended ac operating conditions (v cc = 5v 10%, ta = 0~70 c) (notes 6,7,8) symbol parameter tc5117400bsj/bst unit notes -60 -70 min max. min max t rc random read or write cycle time 110 - 130 - ns t rmw read-modify-write cycle 155 - 180 - ns t pc fast page mode cycle time 40 - 45 - ns t prmw fast page mode read-modify-write cycle time 85 - 95 - ns t rac access time from ras -60-70 ns 9,14, 15 t cac access time from cas - 15 - 20 ns 9,14 t aa access time from column address - 30 - 35 ns 9,15 t cpa access time from cas precharge - 35 - 40 - 9 t clz cas to output in low-z 0 - 0 - ns 9 t off output buffer turn-off delay 0 15 0 15 ns 10 t t transition time (rise and fall) 3 50 3 50 ns 8 t rp ras precharge time 40 - 50 - ns t ras ras pulse width 60 10,000 70 10,000 ns t rasp ras pulse width (fast page mode) 60 200,000 70 200,000 ns t rsh ras hold time 15 - 20 - ns t rhcp ras hold time from cas precharge (fast page mode) 35-40- ns t csh cas hold time 60 - 70 - ns t cas cas pulse width 15 10,000 20 10,000 ns t rcd ras to cas delay time 20 45 20 50 ns 14 t rad ras to column address delay time 15 30 15 35 ns 15 t crp cas to ras precharge time 5 - 5 ns t cp cas precharge time 10 - 10 - ns t asr row address set-up time 0 - 0 - ns t rah row address hold time 10 - 10 - ns t asc column address set-up time 0 - 0 - ns t cah column address hold time 10 - 15 - ns t ral column address to ras lead time 30 - 35 - ns t rcs read command set-up time 0 - 0 - ns t rch read command hold time 0 - 0 - ns 11 t rrh read command hold time referenced to ras 0-0- ns11
tc5117400bsj/bst-60/70 standard dram dr16040794 6 toshiba america electronic components, inc . preliminary electrical characteristics and recommended ac operating conditions (cont) symbol parameter tc5117400bsj/bst unit notes -60 -70 min max. min max t wch write command hold time 10 - 15 - ns t wp write command pulse width 10 - 15 - ns t rwl write command to ras lead time 15 - 20 - ns t cwl write command to cas lead time 15 - 20 - ns t ds data set-up time 0 - 0 - ns 12 t dh data hold time 10 - 15 - ns 12 t ref refresh period - 32 - 32 ms t wcs write command set-up time 0 - 0 - ns 13 t cwd cas to we delay time 40 - 45 - ns 13 t rwd ras to we delay time 85 - 95 - ns 13 t awd column address to we delay time 55 - 60 - ns 13 t cpwd cas precharge to we delay time 60 - 65 - ns 13 t csr cas set-up time (cas before ras cycle) 5-5-ns t chr cas hold time (cas before ras cycle) 10-15- ns t rpc ras to cas precharge time 5 - 5 - ns t cpt cas precharge time (cas before ras counter test cycle 20-30- ns t roh ras hold time referenced to oe 10-10- ns t oea oe access time - 15 - 20 ns t oed oe to data delay 15 - 15 - ns t oez output buffer turn off delay time from oe 015015ns 10 t oeh oe command hold time 10 - 15 - ns t ods output disable setup time 0 - 0 - ns t wts write command set-up time (test mode in) 10-10- ns t wth write command hold time (test mode in) 10-10- ns t wrp we to ras precharge time (cas before ras cycle) 10-10- ns t wrh we to ras hold time (cas before ras cycle) 10-10- ns
dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 7 preliminary electrical characteristics and recommended ac operating conditions in the test mode capacitance (v cc = 5v 10%, f = 1mhz, ta = 0 ~ 70 c) symbol parameter tc5117400bsj/bst unit notes -60 -70 min max. min max t rc random read or write cycle time 115 - 135 - ns t pc fast page mode cycle time 45 - 50 - ns t rac access time from ras -65-75ns 9, 14, 15 t cac access time from cas - 20 - 25 ns 9, 14 t aa access time from column address - 35 - 40 ns 9, 15 t cpa access time from cas precharge - 40 - 45 ns 9 t ras ras pulse width 65 10,000 75 10,000 ns t rasp ras pulse width (fast page mode) 65 200,000 75 200,000 ns t rsh ras hold time 20 - 25 - ns t csh cas hold time 65 - 75 - ns t rhcp cas precharge to ras hold 40 - 45 - ns t cas cas pulse width 20 10,000 25 10,000 ns t ral column address to ras lead time 35 - 40 - ns symbol parameter min max unit c i1 input capacitance (a0~a10) - 5 p f c i2 input capacitance (ras , cas , we , oe )-7 c o input capacitance (i/o1~i/o4) - 7
tc5117400bsj/bst-60/70 standard dram dr16040794 8 toshiba america electronic components, inc . preliminary notes: 1. stresses greater than those listed under ?bsolute maximum ratings?may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. i cc1 , i cc3 , i cc4 , i cc6 depend on cycle rate. 4. i cc1 , i cc4 depend on output loading. speci?d values are obtained with the output open. 5. address can be changed one or less while ras =v il . in case of i cc4 , it can be changed once or less during a fast page mode cycle (t pc ). 6. an initial pause of 200 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles are required. 7. ac measurements assume t t =5ns. 8. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 9. measured with a load equivalent to 2 ttl loads and 100pf. 10. t off (max.) de?es the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 11. either t rch or t rrh must be satis?d for a read cycle. 12. these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-modify-write cycles. 13. t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), (fast page mode), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell: if neither of the above sets of conditions are satis?d, the condition of the data out (at access time) is indeterminate. 14. operation within the t rcd (max.) limit insures that t rac can be met. t rcd (max.) is speci?d as a reference point only: if t rcd is greater than the speci?d t rcd (max.) limit, then access time is controlled by t cac . 15. operation within the t rad (max.) limit insures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only: if t rad is greater than the speci?d t rad (max.) limit, then access time is controlled by t aa .
dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 9 preliminary timing waveforms read cycle
tc5117400bsj/bst-60/70 standard dram dr16040794 10 toshiba america electronic components, inc . preliminary write cycle (early write)
dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 11 preliminary write cycle (oe controlled write)
tc5117400bsj/bst-60/70 standard dram dr16040794 12 toshiba america electronic components, inc . preliminary read-modify-write cycle
dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 13 preliminary fast page mode read cycle
tc5117400bsj/bst-60/70 standard dram dr16040794 14 toshiba america electronic components, inc . preliminary fast page mode write cycle (early write)
dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 15 preliminary fast page mode read-modify-write cycle
tc5117400bsj/bst-60/70 standard dram dr16040794 16 toshiba america electronic components, inc . preliminary ras only refresh cycle cas before ras refresh cycle
dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 17 preliminary hidden refresh cycle (read)
tc5117400bsj/bst-60/70 standard dram dr16040794 18 toshiba america electronic components, inc . preliminary hidden refresh cycle (write)
dr16040794 standard dram tc5117400bsj/bst-60/70 toshiba america electronic components, inc . 19 preliminary outline drawings (soj26-p-300c) unit in mm
tc5117400bsj/bst-60/70 standard dram dr16040794 20 toshiba america electronic components, inc . preliminary outline drawings (tsop26-p-300d) unit in mm
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